The use of error detection schemes to detect bus failure is common throughout the electronic industry. Bus error detection techniques typically involve the use of error detection codes or parity bits to detect single bit errors in the data being sent over the bus. Since buses are generally reliable, the use of more elaborate error detection techniques is not common. Typically, the bus failure rate is used as a factor in determining the Mean Time Between Failure (MTBF) of the systems in which error detection techniques are incorporated rather than attempting to increase bus reliability. All known systems detect error or bus failure only after the address information or data has been transmitted and received. This after the fact detection of bus failure results in lost data and data recovery problems.
A fault tolerant bus which provides the address lines for a memory is particularly difficult to implement. In such a system, any address error correction procedures would have to be incorporated into the memory device itself in order to provide for the correction of errors which affect only one memory device. Such error detection schemes can include Hamming codes. Other prior art systems using error correction codes exist which can recover data when up to two random access memories (RAM) fail.
These prior art systems fail to detect certain types of addressing errors which can simultaneously affect more than two RAM arrays. The sources of these errors can include open circuited bus drivers and open circuits of the etch between the bus drivers and the memories.